LXC/DRC Container Memif

This section includes summary graphs of VPP Phy-to-Phy packet latency with Container memif Connections measured at 100% of discovered NDR throughput rate. Latency is reported for VPP running in multiple configurations of VPP worker thread(s), a.k.a. VPP data plane thread(s), and their physical CPU core(s) placement.

CSIT source code for the test cases used for plots can be found in CSIT git repository.

3n-hsw-x520

64b-1t1c-base_and_scale

Latency: memif-3n-hsw-x520-64b-1t1c-base_and_scale-ndr



64b-2t2c-base_and_scale

Latency: memif-3n-hsw-x520-64b-2t2c-base_and_scale-ndr



3n-hsw-x710

64b-1t1c-base_and_scale

Latency: memif-3n-hsw-x710-64b-1t1c-base_and_scale-ndr



64b-2t2c-base_and_scale

Latency: memif-3n-hsw-x710-64b-2t2c-base_and_scale-ndr



3n-hsw-xl710

64b-1t1c-base_and_scale

Latency: memif-3n-hsw-xl710-64b-1t1c-base_and_scale-ndr



64b-2t2c-base_and_scale

Latency: memif-3n-hsw-xl710-64b-2t2c-base_and_scale-ndr



3n-skx-x710

64b-2t1c-base_and_scale

Latency: memif-3n-skx-x710-64b-2t1c-base_and_scale-ndr



64b-4t2c-base_and_scale

Latency: memif-3n-skx-x710-64b-4t2c-base_and_scale-ndr