Testpmd

This section includes summary graphs of Testpmd Phy-to-Phy packet latency with L2 Ethernet Interface Loop measured at 100% of discovered NDR throughput rate. Latency is reported for Testpmd running in multiple configurations of Testpmd pmd thread(s), a.k.a. Testpmd data plane thread(s), and their physical CPU core(s) placement.

CSIT source code for the test cases used for plots can be found in CSIT git repository.

3n-hsw-x520

64b-1t1c-base


64b-2t2c-base


3n-hsw-x710

64b-1t1c-base


64b-2t2c-base


3n-hsw-xl710

64b-1t1c-base


64b-2t2c-base


3n-skx-x710

64b-2t1c-base


64b-4t2c-base


3n-skx-xxv710

64b-2t1c-base


64b-4t2c-base


2n-skx-x710

64b-2t1c-base


64b-4t2c-base


2n-skx-xxv710

64b-2t1c-base


64b-4t2c-base