16 #ifndef __perfmon_intel_h 17 #define __perfmon_intel_h 19 #define PERF_INTEL_CODE(event, umask, edge, any, inv, cmask) \ 20 ((event) | (umask) << 8 | (edge) << 18 | (any) << 21 | (inv) << 23 | \ 25 #define foreach_perf_intel_core_event \ 26 _ (0x00, 0x02, 0, 0, 0, 0x00, CPU_CLK_UNHALTED, THREAD, \ 27 "Core cycles when the thread is not in halt state") \ 28 _ (0x00, 0x03, 0, 0, 0, 0x00, CPU_CLK_UNHALTED, REF_TSC, \ 29 "Reference cycles when the core is not in halt state.") \ 30 _ (0x00, 0x04, 0, 0, 0, 0x00, TOPDOWN, SLOTS, \ 31 "TMA slots available for an unhalted logical processor.") \ 32 _ (0x00, 0x80, 0, 0, 0, 0x00, TOPDOWN, L1_METRICS, \ 33 "TMA slots metrics for an unhalted logical processor.") \ 34 _ (0x03, 0x02, 0, 0, 0, 0x00, LD_BLOCKS, STORE_FORWARD, \ 35 "Loads blocked due to overlapping with a preceding store that cannot be" \ 37 _ (0x03, 0x08, 0, 0, 0, 0x00, LD_BLOCKS, NO_SR, \ 38 "The number of times that split load operations are temporarily " \ 40 "because all resources for handling the split accesses are in use.") \ 41 _ (0x07, 0x01, 0, 0, 0, 0x00, LD_BLOCKS_PARTIAL, ADDRESS_ALIAS, \ 42 "False dependencies in MOB due to partial compare on address.") \ 43 _ (0x08, 0x01, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, MISS_CAUSES_A_WALK, \ 44 "Load misses in all DTLB levels that cause page walks") \ 45 _ (0x08, 0x02, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED_4K, \ 46 "Page walk completed due to a demand data load to a 4K page") \ 47 _ (0x08, 0x04, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED_2M_4M, \ 48 "Page walk completed due to a demand data load to a 2M/4M page") \ 49 _ (0x08, 0x08, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED_1G, \ 50 "Page walk completed due to a demand data load to a 1G page") \ 51 _ (0x08, 0x0E, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED, \ 52 "Load miss in all TLB levels causes a page walk that completes. (All " \ 54 _ (0x08, 0x10, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_PENDING, \ 55 "Counts 1 per cycle for each PMH that is busy with a page walk for a " \ 56 "load. EPT page walk duration are excluded in Skylake.") \ 57 _ (0x08, 0x20, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, STLB_HIT, \ 58 "Loads that miss the DTLB and hit the STLB.") \ 59 _ (0x0D, 0x01, 0, 0, 0, 0x00, INT_MISC, RECOVERY_CYCLES, \ 60 "Core cycles the allocator was stalled due to recovery from earlier " \ 61 "clear event for this thread (e.g. misprediction or memory nuke)") \ 62 _ (0x0E, 0x01, 0, 0, 0, 0x00, UOPS_ISSUED, ANY, \ 63 "Uops that Resource Allocation Table (RAT) issues to Reservation " \ 65 _ (0x28, 0x07, 0, 0, 0, 0x00, CORE_POWER, LVL0_TURBO_LICENSE, \ 66 "Core cycles where the core was running in a manner where Turbo may be " \ 67 "clipped to the Non-AVX turbo schedule.") \ 68 _ (0x28, 0x18, 0, 0, 0, 0x00, CORE_POWER, LVL1_TURBO_LICENSE, \ 69 "Core cycles where the core was running in a manner where Turbo may be " \ 70 "clipped to the AVX2 turbo schedule.") \ 71 _ (0x28, 0x20, 0, 0, 0, 0x00, CORE_POWER, LVL2_TURBO_LICENSE, \ 72 "Core cycles where the core was running in a manner where Turbo may be " \ 73 "clipped to the AVX512 turbo schedule.") \ 74 _ (0x28, 0x40, 0, 0, 0, 0x00, CORE_POWER, THROTTLE, \ 75 "Core cycles the core was throttled due to a pending power level " \ 77 _ (0x3C, 0x00, 0, 0, 0, 0x00, CPU_CLK_UNHALTED, THREAD_P, \ 78 "Thread cycles when thread is not in halt state") \ 79 _ (0x3C, 0x00, 0, 1, 0, 0x00, CPU_CLK_UNHALTED, THREAD_P_ANY, \ 80 "Core cycles when at least one thread on the physical core is not in " \ 82 _ (0x3C, 0x00, 1, 0, 0, 0x01, CPU_CLK_UNHALTED, RING0_TRANS, \ 83 "Counts when there is a transition from ring 1, 2 or 3 to ring 0.") \ 84 _ (0x48, 0x01, 0, 0, 0, 0x01, L1D_PEND_MISS, PENDING_CYCLES, \ 85 "Cycles with L1D load Misses outstanding.") \ 86 _ (0x48, 0x01, 0, 0, 0, 0x00, L1D_PEND_MISS, PENDING, \ 87 "L1D miss outstandings duration in cycles") \ 88 _ (0x48, 0x02, 0, 0, 0, 0x00, L1D_PEND_MISS, FB_FULL, \ 89 "Number of times a request needed a FB entry but there was no entry " \ 90 "available for it. That is the FB unavailability was dominant reason " \ 91 "for blocking the request. A request includes cacheable/uncacheable " \ 92 "demands that is load, store or SW prefetch.") \ 93 _ (0x51, 0x01, 0, 0, 0, 0x00, L1D, REPLACEMENT, \ 94 "L1D data line replacements") \ 95 _ (0x51, 0x04, 0, 0, 0, 0x00, L1D, M_EVICT, "L1D data line evictions") \ 96 _ (0x83, 0x02, 0, 0, 0, 0x00, ICACHE_64B, IFTAG_MISS, \ 97 "Instruction fetch tag lookups that miss in the instruction cache " \ 98 "(L1I). Counts at 64-byte cache-line granularity.") \ 99 _ (0x9C, 0x01, 0, 0, 0, 0x00, IDQ_UOPS_NOT_DELIVERED, CORE, \ 100 "Uops not delivered to Resource Allocation Table (RAT) per thread when " \ 101 "backend of the machine is not stalled") \ 102 _ (0xC0, 0x00, 0, 0, 0, 0x00, INST_RETIRED, ANY_P, \ 103 "Number of instructions retired. General Counter - architectural event") \ 104 _ (0xC2, 0x02, 0, 0, 0, 0x00, UOPS_RETIRED, RETIRE_SLOTS, \ 105 "Retirement slots used.") \ 106 _ (0xC4, 0x00, 0, 0, 0, 0x00, BR_INST_RETIRED, ALL_BRANCHES, \ 107 "Counts all (macro) branch instructions retired.") \ 108 _ (0xC5, 0x00, 0, 0, 0, 0x00, BR_MISP_RETIRED, ALL_BRANCHES, \ 109 "All mispredicted macro branch instructions retired.") \ 110 _ (0xC4, 0x20, 0, 0, 0, 0x00, BR_INST_RETIRED, NEAR_TAKEN, \ 111 "Taken branch instructions retired.") \ 112 _ (0xD0, 0x81, 0, 0, 0, 0x00, MEM_INST_RETIRED, ALL_LOADS, \ 113 "All retired load instructions.") \ 114 _ (0xD0, 0x82, 0, 0, 0, 0x00, MEM_INST_RETIRED, ALL_STORES, \ 115 "All retired store instructions.") \ 116 _ (0xD1, 0x01, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L1_HIT, \ 117 "Retired load instructions with L1 cache hits as data sources") \ 118 _ (0xD1, 0x02, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L2_HIT, \ 119 "Retired load instructions with L2 cache hits as data sources") \ 120 _ (0xD1, 0x04, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L3_HIT, \ 121 "Retired load instructions with L3 cache hits as data sources") \ 122 _ (0xD1, 0x08, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L1_MISS, \ 123 "Retired load instructions missed L1 cache as data sources") \ 124 _ (0xD1, 0x10, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L2_MISS, \ 125 "Retired load instructions missed L2 cache as data sources") \ 126 _ (0xD1, 0x20, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L3_MISS, \ 127 "Retired load instructions missed L3 cache as data sources") \ 128 _ (0xD1, 0x40, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, FB_HIT, \ 129 "Retired load instructions which data sources were load missed L1 but " \ 130 "hit FB due to preceding miss to the same cache line with data not " \ 132 _ (0xD2, 0x01, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_MISS, \ 133 "Retired load instructions which data sources were L3 hit and cross-" \ 134 "core snoop missed in on-pkg core cache.") \ 135 _ (0xD2, 0x02, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_HIT, \ 136 "Retired load instructions which data sources were L3 and cross-core " \ 137 "snoop hits in on-pkg core cache") \ 138 _ (0xD2, 0x04, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_HITM, \ 139 "Retired load instructions which data sources were HitM responses from " \ 141 _ (0xD2, 0x08, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_NONE, \ 142 "Retired load instructions which data sources were hits in L3 without " \ 144 _ (0xD3, 0x01, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, LOCAL_DRAM, \ 145 "Retired load instructions which data sources missed L3 but serviced " \ 147 _ (0xD3, 0x02, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, REMOTE_DRAM, \ 148 "Retired load instructions which data sources missed L3 but serviced " \ 149 "from remote dram") \ 150 _ (0xD3, 0x04, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, REMOTE_HITM, \ 151 "Retired load instructions whose data sources was remote HITM") \ 152 _ (0xD3, 0x08, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, REMOTE_FWD, \ 153 "Retired load instructions whose data sources was forwarded from a " \ 155 _ (0xF0, 0x40, 0, 0, 0, 0x00, L2_TRANS, L2_WB, \ 156 "L2 writebacks that access L2 cache") \ 157 _ (0xF1, 0x1F, 0, 0, 0, 0x00, L2_LINES_IN, ALL, \ 158 "L2 cache lines filling L2") \ 159 _ (0xFE, 0x02, 0, 0, 0, 0x00, IDI_MISC, WB_UPGRADE, \ 160 "Counts number of cache lines that are allocated and written back to L3" \ 161 " with the intention that they are more likely to be reused shortly") \ 162 _ (0xFE, 0x04, 0, 0, 0, 0x00, IDI_MISC, WB_DOWNGRADE, \ 163 "Counts number of cache lines that are dropped and not written back to " \ 164 "L3 as they are deemed to be less likely to be reused shortly") 168 #define _(event, umask, edge, any, inv, cmask, name, suffix, desc) \ 169 INTEL_CORE_E_##name##_##suffix, #define foreach_perf_intel_core_event