FD.io VPP  v19.04.4-rc0-5-ge88582fac
Vector Packet Processing
pci_config.h
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1 /*
2  * Copyright (c) 2016 Cisco and/or its affiliates.
3  * Licensed under the Apache License, Version 2.0 (the "License");
4  * you may not use this file except in compliance with the License.
5  * You may obtain a copy of the License at:
6  *
7  * http://www.apache.org/licenses/LICENSE-2.0
8  *
9  * Unless required by applicable law or agreed to in writing, software
10  * distributed under the License is distributed on an "AS IS" BASIS,
11  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  * See the License for the specific language governing permissions and
13  * limitations under the License.
14  */
15 /*
16  * pci.h: PCI definitions.
17  *
18  * Copyright (c) 2008 Eliot Dresselhaus
19  *
20  * Permission is hereby granted, free of charge, to any person obtaining
21  * a copy of this software and associated documentation files (the
22  * "Software"), to deal in the Software without restriction, including
23  * without limitation the rights to use, copy, modify, merge, publish,
24  * distribute, sublicense, and/or sell copies of the Software, and to
25  * permit persons to whom the Software is furnished to do so, subject to
26  * the following conditions:
27  *
28  * The above copyright notice and this permission notice shall be
29  * included in all copies or substantial portions of the Software.
30  *
31  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
33  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
35  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
36  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
37  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
38  */
39 
40 #ifndef included_vlib_pci_config_h
41 #define included_vlib_pci_config_h
42 
43 #include <vppinfra/byte_order.h>
44 #include <vppinfra/error.h>
45 
46 typedef enum
47 {
50 
58 
65 
71 
77 
81  PCI_CLASS_MEMORY = 0x0500,
82 
93  PCI_CLASS_BRIDGE = 0x0600,
94 
101 
109 
116  PCI_CLASS_INPUT = 0x0900,
117 
121 
130 
138 
141 
147 
151  PCI_CLASS_CRYPT = 0x1000,
152 
155  PCI_CLASS_SP = 0x1100,
157 
158 static inline pci_device_class_t
160 {
161  return c & ~0xff;
162 }
163 
164 /*
165  * 0x1000 is the legacy device-id value
166  * 0x1041 is (0x1040 + 1), 1 being the Virtio Device ID
167  */
168 #define VIRTIO_PCI_LEGACY_DEVICEID_NET 0x1000
169 #define VIRTIO_PCI_MODERN_DEVICEID_NET 0x1041
170 
171 /*
172  * Under PCI, each device has 256 bytes of configuration address space,
173  * of which the first 64 bytes are standardized as follows:
174  */
175 typedef struct
176 {
179 
181 #define PCI_COMMAND_IO (1 << 0) /* Enable response in I/O space */
182 #define PCI_COMMAND_MEMORY (1 << 1) /* Enable response in Memory space */
183 #define PCI_COMMAND_BUS_MASTER (1 << 2) /* Enable bus mastering */
184 #define PCI_COMMAND_SPECIAL (1 << 3) /* Enable response to special cycles */
185 #define PCI_COMMAND_WRITE_INVALIDATE (1 << 4) /* Use memory write and invalidate */
186 #define PCI_COMMAND_VGA_PALETTE_SNOOP (1 << 5)
187 #define PCI_COMMAND_PARITY (1 << 6)
188 #define PCI_COMMAND_WAIT (1 << 7) /* Enable address/data stepping */
189 #define PCI_COMMAND_SERR (1 << 8) /* Enable SERR */
190 #define PCI_COMMAND_BACK_TO_BACK_WRITE (1 << 9)
191 #define PCI_COMMAND_INTX_DISABLE (1 << 10) /* INTx Emulation Disable */
192 
194 #define PCI_STATUS_INTX_PENDING (1 << 3)
195 #define PCI_STATUS_CAPABILITY_LIST (1 << 4)
196 #define PCI_STATUS_66MHZ (1 << 5) /* Support 66 Mhz PCI 2.1 bus */
197 #define PCI_STATUS_UDF (1 << 6) /* Support User Definable Features (obsolete) */
198 #define PCI_STATUS_BACK_TO_BACK_WRITE (1 << 7) /* Accept fast-back to back */
199 #define PCI_STATUS_PARITY_ERROR (1 << 8) /* Detected parity error */
200 #define PCI_STATUS_DEVSEL_GET(x) ((x >> 9) & 3) /* DEVSEL timing */
201 #define PCI_STATUS_DEVSEL_FAST (0 << 9)
202 #define PCI_STATUS_DEVSEL_MEDIUM (1 << 9)
203 #define PCI_STATUS_DEVSEL_SLOW (2 << 9)
204 #define PCI_STATUS_SIG_TARGET_ABORT (1 << 11) /* Set on target abort */
205 #define PCI_STATUS_REC_TARGET_ABORT (1 << 12) /* Master ack of " */
206 #define PCI_STATUS_REC_MASTER_ABORT (1 << 13) /* Set on master abort */
207 #define PCI_STATUS_SIG_SYSTEM_ERROR (1 << 14) /* Set when we drive SERR */
208 #define PCI_STATUS_DETECTED_PARITY_ERROR (1 << 15)
209 
211  u8 programming_interface_class; /* Reg. Level Programming Interface */
212 
214 
217 
219 #define PCI_HEADER_TYPE_NORMAL 0
220 #define PCI_HEADER_TYPE_BRIDGE 1
221 #define PCI_HEADER_TYPE_CARDBUS 2
222 
224 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
225 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
226 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
228 
229 /* Byte swap config header. */
230 always_inline void
232 {
234  return;
235 #define _(f,t) r->f = clib_byte_swap_##t (r->f)
236  _(vendor_id, u16);
237  _(device_id, u16);
238  _(command, u16);
239  _(status, u16);
240  _(device_class, u16);
241 #undef _
242 }
243 
244 /* Header type 0 (normal devices) */
245 typedef struct
246 {
248 
249  /*
250  * Base addresses specify locations in memory or I/O space.
251  * Decoded size can be determined by writing a value of
252  * 0xffffffff to the register, and reading it back. Only
253  * 1 bits are decoded.
254  */
255  u32 base_address[6];
256 
258 
261 
263 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
264 #define PCI_ROM_ADDRESS_ENABLE 0x01
265 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
266 
268  CLIB_PAD_FROM_TO (0x35, 0x3c);
269 
274 
275  u8 capability_data[0];
277 
278 always_inline void
280 {
281  int i;
283  return;
285 #define _(f,t) r->f = clib_byte_swap_##t (r->f)
286  for (i = 0; i < ARRAY_LEN (r->base_address); i++)
287  _(base_address[i], u32);
288  _(cardbus_cis, u16);
289  _(subsystem_vendor_id, u16);
290  _(subsystem_id, u16);
291  _(rom_address, u32);
292 #undef _
293 }
294 
295 /* Header type 1 (PCI-to-PCI bridges) */
296 typedef struct
297 {
299 
300  u32 base_address[2];
301 
302  /* Primary/secondary bus number. */
305 
306  /* Highest bus number behind the bridge */
308 
310 
311  /* I/O range behind bridge. */
312  u8 io_base, io_limit;
313 
314  /* Secondary status register, only bit 14 used */
316 
317  /* Memory range behind bridge in units of 64k bytes. */
318  u16 memory_base, memory_limit;
319 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
320 #define PCI_MEMORY_RANGE_MASK (~0x0fUL)
321 
322  u16 prefetchable_memory_base, prefetchable_memory_limit;
323 #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
324 #define PCI_PREF_RANGE_TYPE_32 0x00
325 #define PCI_PREF_RANGE_TYPE_64 0x01
326 #define PCI_PREF_RANGE_MASK (~0x0fUL)
327 
332 
333  /* Same as for type 0. */
335  CLIB_PAD_FROM_TO (0x35, 0x37);
336 
338  CLIB_PAD_FROM_TO (0x3c, 0x3e);
339 
341 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
342 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
343 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
344 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
345 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
346 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
347 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
348 
349  u8 capability_data[0];
351 
352 always_inline void
354 {
355  int i;
357  return;
359 #define _(f,t) r->f = clib_byte_swap_##t (r->f)
360  for (i = 0; i < ARRAY_LEN (r->base_address); i++)
361  _(base_address[i], u32);
362  _(secondary_status, u16);
363  _(memory_base, u16);
364  _(memory_limit, u16);
365  _(prefetchable_memory_base, u16);
366  _(prefetchable_memory_limit, u16);
367  _(prefetchable_memory_base_upper_32bits, u32);
368  _(prefetchable_memory_limit_upper_32bits, u32);
369  _(io_base_upper_16bits, u16);
370  _(io_limit_upper_16bits, u16);
371  _(rom_address, u32);
372  _(bridge_control, u16);
373 #undef _
374 }
375 
376 /* Capabilities. */
378 {
379  /* Power Management */
381 
382  /* Accelerated Graphics Port */
384 
385  /* Vital Product Data */
387 
388  /* Slot Identification */
390 
391  /* Message Signalled Interrupts */
393 
394  /* CompactPCI HotSwap */
396 
397  /* PCI-X */
399 
400  /* Hypertransport. */
402 
403  /* PCI Standard Hot-Plug Controller */
405 
406  /* PCI Express */
408 
409  /* MSI-X */
412 
413 /* Common header for capabilities. */
414 typedef struct
415 {
416  enum pci_capability_type type:8;
417  u8 next_offset;
418 } __clib_packed pci_capability_regs_t;
419 
420 always_inline void *
422 {
423  pci_capability_regs_t *c;
424  u32 next_offset;
425  u32 ttl = 48;
426 
428  return 0;
429 
430  next_offset = t->first_capability_offset;
431  while (ttl-- && next_offset >= 0x40)
432  {
433  c = (void *) t + (next_offset & ~3);
434  if ((u8) c->type == 0xff)
435  break;
436  if (c->type == cap_type)
437  return c;
438  next_offset = c->next_offset;
439  }
440  return 0;
441 }
442 
443 /* Power Management Registers */
444 typedef struct
445 {
446  pci_capability_regs_t header;
447  u16 capabilities;
448 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
449 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
450 #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
451 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
452 #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
453 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
454 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
455 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
456 #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
457 #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
458 #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
459 #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
460 #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
461 #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
462  u16 control;
463 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
464 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
465 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
466 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
467 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
468  u8 extensions;
469 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
470 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
471  u8 data;
472 } __clib_packed pci_power_management_regs_t;
473 
474 /* AGP registers */
475 typedef struct
476 {
477  pci_capability_regs_t header;
478  u8 version;
479  u8 rest_of_capability_flags;
480  u32 status;
481  u32 command;
482  /* Command & status common bits. */
483 #define PCI_AGP_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
484 #define PCI_AGP_SBA 0x0200 /* Sideband addressing supported */
485 #define PCI_AGP_64BIT 0x0020 /* 64-bit addressing supported */
486 #define PCI_AGP_ALLOW_TRANSACTIONS 0x0100 /* Allow processing of AGP transactions */
487 #define PCI_AGP_FW 0x0010 /* FW transfers supported/forced */
488 #define PCI_AGP_RATE4 0x0004 /* 4x transfer rate supported */
489 #define PCI_AGP_RATE2 0x0002 /* 2x transfer rate supported */
490 #define PCI_AGP_RATE1 0x0001 /* 1x transfer rate supported */
491 } __clib_packed pci_agp_regs_t;
492 
493 /* Vital Product Data */
494 typedef struct
495 {
496  pci_capability_regs_t header;
497  u16 address;
498 #define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
499 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
500  u32 data;
501 } __clib_packed pci_vpd_regs_t;
502 
503 /* Slot Identification */
504 typedef struct
505 {
506  pci_capability_regs_t header;
507  u8 esr;
508 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
509 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
510  u8 chassis;
511 } __clib_packed pci_sid_regs_t;
512 
513 /* Message Signalled Interrupts registers */
514 typedef struct
515 {
516  pci_capability_regs_t header;
517  u16 flags;
518 #define PCI_MSI_FLAGS_ENABLE (1 << 0) /* MSI feature enabled */
519 #define PCI_MSI_FLAGS_GET_MAX_QUEUE_SIZE(x) ((x >> 1) & 0x7)
520 #define PCI_MSI_FLAGS_MAX_QUEUE_SIZE(x) (((x) & 0x7) << 1)
521 #define PCI_MSI_FLAGS_GET_QUEUE_SIZE(x) ((x >> 4) & 0x7)
522 #define PCI_MSI_FLAGS_QUEUE_SIZE(x) (((x) & 0x7) << 4)
523 #define PCI_MSI_FLAGS_64BIT (1 << 7) /* 64-bit addresses allowed */
524 #define PCI_MSI_FLAGS_MASKBIT (1 << 8) /* 64-bit mask bits allowed */
525  u32 address;
526  u32 data;
527  u32 mask_bits;
528 } __clib_packed pci_msi32_regs_t;
529 
530 typedef struct
531 {
532  pci_capability_regs_t header;
533  u16 flags;
534  u32 address[2];
535  u32 data;
536  u32 mask_bits;
537 } __clib_packed pci_msi64_regs_t;
538 
539 /* CompactPCI Hotswap Register */
540 typedef struct
541 {
542  pci_capability_regs_t header;
543  u16 control_status;
544 #define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
545 #define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
546 #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
547 #define PCI_CHSWP_LOO 0x08 /* LED On / Off */
548 #define PCI_CHSWP_PI 0x30 /* Programming Interface */
549 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
550 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
551 } __clib_packed pci_chswp_regs_t;
552 
553 /* PCIX registers */
554 typedef struct
555 {
556  pci_capability_regs_t header;
557  u16 command;
558 #define PCIX_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
559 #define PCIX_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
560 #define PCIX_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
561 #define PCIX_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
562 #define PCIX_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
563  u32 status;
564 #define PCIX_STATUS_DEVFN 0x000000ff /* A copy of devfn */
565 #define PCIX_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
566 #define PCIX_STATUS_64BIT 0x00010000 /* 64-bit device */
567 #define PCIX_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
568 #define PCIX_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
569 #define PCIX_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
570 #define PCIX_STATUS_COMPLEX 0x00100000 /* Device Complexity */
571 #define PCIX_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
572 #define PCIX_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
573 #define PCIX_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
574 #define PCIX_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
575 #define PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
576 #define PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
577 } __clib_packed pcix_config_regs_t;
578 
579 static inline int
580 pcie_size_to_code (int bytes)
581 {
582  ASSERT (is_pow2 (bytes));
583  ASSERT (bytes <= 4096);
584  return min_log2 (bytes) - 7;
585 }
586 
587 static inline int
589 {
590  int size = 1 << (code + 7);
591  ASSERT (size <= 4096);
592  return size;
593 }
594 
595 /* PCI Express capability registers */
596 typedef struct
597 {
598  pci_capability_regs_t header;
599  u16 pcie_capabilities;
600 #define PCIE_CAP_VERSION(x) (((x) >> 0) & 0xf)
601 #define PCIE_CAP_DEVICE_TYPE(x) (((x) >> 4) & 0xf)
602 #define PCIE_DEVICE_TYPE_ENDPOINT 0
603 #define PCIE_DEVICE_TYPE_LEGACY_ENDPOINT 1
604 #define PCIE_DEVICE_TYPE_ROOT_PORT 4
605  /* Upstream/downstream port of PCI Express switch. */
606 #define PCIE_DEVICE_TYPE_SWITCH_UPSTREAM 5
607 #define PCIE_DEVICE_TYPE_SWITCH_DOWNSTREAM 6
608 #define PCIE_DEVICE_TYPE_PCIE_TO_PCI_BRIDGE 7
609 #define PCIE_DEVICE_TYPE_PCI_TO_PCIE_BRIDGE 8
610  /* Root complex integrated endpoint. */
611 #define PCIE_DEVICE_TYPE_ROOT_COMPLEX_ENDPOINT 9
612 #define PCIE_DEVICE_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10
613 #define PCIE_CAP_SLOW_IMPLEMENTED (1 << 8)
614 #define PCIE_CAP_MSI_IRQ(x) (((x) >> 9) & 0x1f)
615  u32 dev_capabilities;
616 #define PCIE_DEVCAP_MAX_PAYLOAD(x) (128 << (((x) >> 0) & 0x7))
617 #define PCIE_DEVCAP_PHANTOM_BITS(x) (((x) >> 3) & 0x3)
618 #define PCIE_DEVCAP_EXTENTED_TAG (1 << 5)
619 #define PCIE_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
620 #define PCIE_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
621 #define PCIE_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
622 #define PCIE_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
623 #define PCIE_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
624 #define PCIE_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
625 #define PCIE_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
626  u16 dev_control;
627 #define PCIE_CTRL_CERE 0x0001 /* Correctable Error Reporting En. */
628 #define PCIE_CTRL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
629 #define PCIE_CTRL_FERE 0x0004 /* Fatal Error Reporting Enable */
630 #define PCIE_CTRL_URRE 0x0008 /* Unsupported Request Reporting En. */
631 #define PCIE_CTRL_RELAX_EN 0x0010 /* Enable relaxed ordering */
632 #define PCIE_CTRL_MAX_PAYLOAD(n) (((n) & 7) << 5)
633 #define PCIE_CTRL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
634 #define PCIE_CTRL_PHANTOM 0x0200 /* Phantom Functions Enable */
635 #define PCIE_CTRL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
636 #define PCIE_CTRL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
637 #define PCIE_CTRL_MAX_READ_REQUEST(n) (((n) & 7) << 12)
638  u16 dev_status;
639 #define PCIE_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
640 #define PCIE_DEVSTA_TRPND 0x20 /* Transactions Pending */
641  u32 link_capabilities;
642  u16 link_control;
643  u16 link_status;
644  u32 slot_capabilities;
645  u16 slot_control;
646  u16 slot_status;
647  u16 root_control;
648 #define PCIE_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
649 #define PCIE_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
650 #define PCIE_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */
651 #define PCIE_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
652 #define PCIE_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
653  u16 root_capabilities;
654  u32 root_status;
655  u32 dev_capabilities2;
656  u16 dev_control2;
657  u16 dev_status2;
658  u32 link_capabilities2;
659  u16 link_control2;
660  u16 link_status2;
661  u32 slot_capabilities2;
662  u16 slot_control2;
663  u16 slot_status2;
664 } __clib_packed pcie_config_regs_t;
665 
666 /* PCI express extended capabilities. */
668 {
674 
675 /* Common header for capabilities. */
676 typedef struct
677 {
678  enum pcie_capability_type type:16;
679  u16 version:4;
680  u16 next_capability:12;
681 } __clib_packed pcie_capability_regs_t;
682 
683 typedef struct
684 {
685  pcie_capability_regs_t header;
686  u32 uncorrectable_status;
687 #define PCIE_ERROR_UNC_LINK_TRAINING (1 << 0)
688 #define PCIE_ERROR_UNC_DATA_LINK_PROTOCOL (1 << 4)
689 #define PCIE_ERROR_UNC_SURPRISE_DOWN (1 << 5)
690 #define PCIE_ERROR_UNC_POISONED_TLP (1 << 12)
691 #define PCIE_ERROR_UNC_FLOW_CONTROL (1 << 13)
692 #define PCIE_ERROR_UNC_COMPLETION_TIMEOUT (1 << 14)
693 #define PCIE_ERROR_UNC_COMPLETER_ABORT (1 << 15)
694 #define PCIE_ERROR_UNC_UNEXPECTED_COMPLETION (1 << 16)
695 #define PCIE_ERROR_UNC_RX_OVERFLOW (1 << 17)
696 #define PCIE_ERROR_UNC_MALFORMED_TLP (1 << 18)
697 #define PCIE_ERROR_UNC_CRC_ERROR (1 << 19)
698 #define PCIE_ERROR_UNC_UNSUPPORTED_REQUEST (1 << 20)
699  u32 uncorrectable_mask;
700  u32 uncorrectable_severity;
701  u32 correctable_status;
702 #define PCIE_ERROR_COR_RX_ERROR (1 << 0)
703 #define PCIE_ERROR_COR_BAD_TLP (1 << 6)
704 #define PCIE_ERROR_COR_BAD_DLLP (1 << 7)
705 #define PCIE_ERROR_COR_REPLAY_ROLLOVER (1 << 8)
706 #define PCIE_ERROR_COR_REPLAY_TIMER (1 << 12)
707 #define PCIE_ERROR_COR_ADVISORY (1 << 13)
708  u32 correctable_mask;
709  u32 control;
710  u32 log[4];
711  u32 root_command;
712  u32 root_status;
713  u16 correctable_error_source;
714  u16 error_source;
715 } __clib_packed pcie_advanced_error_regs_t;
716 
717 /* Virtual Channel */
718 #define PCI_VC_PORT_REG1 4
719 #define PCI_VC_PORT_REG2 8
720 #define PCI_VC_PORT_CTRL 12
721 #define PCI_VC_PORT_STATUS 14
722 #define PCI_VC_RES_CAP 16
723 #define PCI_VC_RES_CTRL 20
724 #define PCI_VC_RES_STATUS 26
725 
726 /* Power Budgeting */
727 #define PCI_PWR_DSR 4 /* Data Select Register */
728 #define PCI_PWR_DATA 8 /* Data Register */
729 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
730 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
731 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
732 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
733 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
734 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
735 #define PCI_PWR_CAP 12 /* Capability */
736 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
737 
738 #endif /* included_vlib_pci_config_h */
739 
740 /*
741  * fd.io coding-style-patch-verification: ON
742  *
743  * Local Variables:
744  * eval: (c-set-style "gnu")
745  * End:
746  */
static pci_device_class_t pci_device_class_base(pci_device_class_t c)
Definition: pci_config.h:159
pci_config_header_t header
Definition: pci_config.h:298
typedef address
Definition: ip_types.api:30
u32 flags
Definition: vhost_user.h:115
pcie_capability_type
Definition: pci_config.h:667
static void * pci_config_find_capability(pci_config_type0_regs_t *t, int cap_type)
Definition: pci_config.h:421
pci_capability_type
Definition: pci_config.h:377
enum pcie_capability_type pcie_capability_type_t
enum pci_capability_type pci_capability_type_t
int i
u8 data[128]
Definition: ipsec.api:248
static void pci_config_header_little_to_host(pci_config_header_t *r)
Definition: pci_config.h:231
unsigned char u8
Definition: types.h:56
static uword min_log2(uword x)
Definition: clib.h:144
static void pci_config_type1_little_to_host(pci_config_type1_regs_t *r)
Definition: pci_config.h:353
#define always_inline
Definition: clib.h:98
unsigned int u32
Definition: types.h:88
static int pcie_size_to_code(int bytes)
Definition: pci_config.h:580
pci_device_class_t
Definition: pci_config.h:46
uword size
unsigned short u16
Definition: types.h:57
static void pci_config_type0_little_to_host(pci_config_type0_regs_t *r)
Definition: pci_config.h:279
svmdb_client_t * c
#define PCI_STATUS_CAPABILITY_LIST
Definition: pci_config.h:195
#define ARRAY_LEN(x)
Definition: clib.h:62
#define ASSERT(truth)
option version
Definition: memclnt.api:17
static uword is_pow2(uword x)
Definition: clib.h:235
#define CLIB_ARCH_IS_BIG_ENDIAN
Definition: byte_order.h:44
u32 prefetchable_memory_limit_upper_32bits
Definition: pci_config.h:329
static int pcie_code_to_size(int code)
Definition: pci_config.h:588
vhost_user_log_t log
Definition: vhost_user.h:123
pci_device_class_t device_class
Definition: pci_config.h:213
u32 prefetchable_memory_base_upper_32bits
Definition: pci_config.h:328
pci_config_header_t header
Definition: pci_config.h:247