FD.io VPP  v17.01-9-ge7dcee4
Vector Packet Processing
cache.h File Reference
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Macros

#define CLIB_LOG2_CACHE_LINE_BYTES   6
 
#define CLIB_CACHE_LINE_BYTES   (1 << CLIB_LOG2_CACHE_LINE_BYTES)
 
#define CLIB_CACHE_LINE_ALIGN_MARK(mark)   u8 mark[0] __attribute__((aligned(CLIB_CACHE_LINE_BYTES)))
 
#define CLIB_PREFETCH_READ   0
 
#define CLIB_PREFETCH_LOAD   0 /* alias for read */
 
#define CLIB_PREFETCH_WRITE   1
 
#define CLIB_PREFETCH_STORE   1 /* alias for write */
 
#define CLIB_PREFETCH(addr, size, type)
 

Macro Definition Documentation

#define CLIB_CACHE_LINE_ALIGN_MARK (   mark)    u8 mark[0] __attribute__((aligned(CLIB_CACHE_LINE_BYTES)))

Definition at line 68 of file cache.h.

#define CLIB_CACHE_LINE_BYTES   (1 << CLIB_LOG2_CACHE_LINE_BYTES)

Definition at line 67 of file cache.h.

#define CLIB_LOG2_CACHE_LINE_BYTES   6

Definition at line 49 of file cache.h.

#define CLIB_PREFETCH (   addr,
  size,
  type 
)
Value:
do { \
void * _addr = (addr); \
_CLIB_PREFETCH (0, size, type); \
_CLIB_PREFETCH (1, size, type); \
_CLIB_PREFETCH (2, size, type); \
_CLIB_PREFETCH (3, size, type); \
} while (0)
bad routing header type(not 4)") sr_error (NO_MORE_SEGMENTS
#define ASSERT(truth)
u64 size
Definition: vhost-user.h:74
vhost_vring_addr_t addr
Definition: vhost-user.h:81
#define CLIB_CACHE_LINE_BYTES
Definition: cache.h:67

Definition at line 82 of file cache.h.

#define CLIB_PREFETCH_LOAD   0 /* alias for read */

Definition at line 72 of file cache.h.

#define CLIB_PREFETCH_READ   0

Definition at line 71 of file cache.h.

#define CLIB_PREFETCH_STORE   1 /* alias for write */

Definition at line 74 of file cache.h.

#define CLIB_PREFETCH_WRITE   1

Definition at line 73 of file cache.h.